• DocumentCode
    2591115
  • Title

    Mixing global and local competition in genetic optimization based design space exploration of analog circuits

  • Author

    Somani, Abhishek ; Chakrabarti, P.P. ; Patra, Amit

  • Author_Institution
    Adv. VLSI Design Lab., Indian Inst. of Technol., Kharagpur, India
  • fYear
    2005
  • fDate
    7-11 March 2005
  • Firstpage
    1064
  • Abstract
    The knowledge of optimal design space boundaries of component circuits can be extremely useful in making good subsystem-level design decisions which are aware of the parasitics and other second-order circuit-level details. However, direct application of popular multi-objective genetic optimization algorithms were found to produce Pareto fronts with poor diversity for analog circuit problems. The paper proposes a novel approach to control the diversity of solutions by partitioning the solution space, using local competition to promote diversity and global competition for convergence, and by controlling the proportion of these two mechanisms by a simulated annealing based formulation. The algorithm was applied to extract numerical results on analog switched capacitor integrator circuits with a wide range of tight specifications. The results are found to be significantly better than traditional GA based uncontrolled optimization methods.
  • Keywords
    MOS analogue integrated circuits; analogue circuits; circuit optimisation; genetic algorithms; integrated circuit design; integrating circuits; simulated annealing; switched capacitor networks; MOS integrated analog systems; Pareto fronts; analog circuits; convergence; design space exploration; diversity; global competition; local competition; multi-objective genetic optimization algorithms; parasitics; second-order circuit-level details; simulated annealing; subsystem-level design decisions; switched capacitor integrator circuits; Analog circuits; Circuit simulation; Design optimization; Genetics; Pareto optimization; Partitioning algorithms; Proportional control; Simulated annealing; Space exploration; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2005. Proceedings
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-2288-2
  • Type

    conf

  • DOI
    10.1109/DATE.2005.208
  • Filename
    1395733