DocumentCode
2591172
Title
Using simulation in semiconductor fabrication
Author
Deosthali, Prabhat ; Gardel, Anne
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1990
fDate
11-12 Sep 1990
Firstpage
22
Lastpage
26
Abstract
The authors describe how the use of simulation technology captures the dynamics and interdependencies of very-large-scale-integration (VLSI) fabrication. A case study of a photolithography cell demonstrates how simulation is used to perform capacity planning to optimize the production line. The emphasis is on identifying the bottleneck areas and evaluating proposed changes to minimize the time to market of proprietary chips
Keywords
VLSI; digital simulation; electronic engineering computing; integrated circuit manufacture; VLSI; bottleneck areas; capacity planning; photolithography cell; semiconductor fabrication; simulation technology; very-large-scale-integration; Analytical models; Capacity planning; Fabrication; Lithography; Optimized production technology; Performance analysis; Production systems; Semiconductor device manufacture; Time to market; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1990. ASMC 90 Proceedings. IEEE/SEMI 1990
Conference_Location
Danvers, MA
Type
conf
DOI
10.1109/ASMC.1990.111215
Filename
111215
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