Automated Pareto analysis for continuously improving a VLSI fabrication area´s process stability

Author

Kielty, Tom ; Delahunty, James

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1990

fDate

11-12 Sep 1990

Firstpage

113

Lastpage

116

Abstract

A software program that automatically creates Pareto diagrams which depict the most unstable electrical test parameters and the most unstable inline process parameters is discussed. The program facilitates the daily decision of which process parameter or electrical test parameter to investigate first. The Pareto diagrams provide a method for quickly determining the statistical stability for each of the process areas or the electrical test area. An implementation of the program is discussed

Keywords

VLSI; electronic engineering computing; integrated circuit technology; integrated circuit testing; Pareto diagrams; VLSI fabrication; electrical test parameter; process stability; software program; statistical stability; unstable electrical test parameters; unstable inline process parameters; Automatic control; Books; Circuit stability; Electronic switching systems; Fabrication; Pareto analysis; Process control; Stability analysis; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1990. ASMC 90 Proceedings. IEEE/SEMI 1990

Conference_Location

Danvers, MA

Type

conf

DOI

10.1109/ASMC.1990.111233

Filename

111233

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2591915