Leakage minimization in cardiac rhythm management devices by time-multiplexing

This paper presents a time-multiplexed architecture of a wavelet based event detector for cardiac rhythm management devices. The architecture of a previously in an ASIC implemented event detector serves as a reference, and is folded in order to minimize area and leakage. Simulation results prove that leakage and dynamic power of the entire design is reduced by more than 30 %, whereas area decreases by 25%. The detector has been routed in 0.13 mum standard low-leakage CMOS technology and is expected to operate below 100 nW.