Evaluation of SystemC modelling of reconfigurable embedded systems

Author

Rissa, Tero ; Donlin, Adam ; Luk, Wayne

Author_Institution

Dept. of Comput., Imperial Coll., London, UK

fYear

2005

fDate

7-11 March 2005

Firstpage

253

Abstract

This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is the MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares register transfer level (RTL) hardware description language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to the 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.

Keywords

C++ language; embedded systems; field programmable gate arrays; industrial property; reconfigurable architectures; system-on-chip; FPGA; MicroBlaze VanillaNet Platform; MicroBlaze uClinux operating system; SystemC modelling; early software development; embedded system design exploration; field programmable gate arrays; pin and cycle accurate models; reconfigurable embedded systems; Design automation; Educational institutions; Embedded computing; Embedded system; Field programmable gate arrays; Hardware design languages; Linux; Operating systems; Programming; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2005. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2288-2

Type

conf

DOI

10.1109/DATE.2005.143

Filename

1395830