Design of SHA-1 Algorithm Based on FPGA

SHA (Secure Hash Algorithm) is a famous message compress standard used in computer cryptography, it can compress a long message to become a short message abstract. The algorithm can be used in many protocols or Secure Algorithm, especially for DSS. In this paper, the improved version SHA-1 is analysised, then improved and implemented in HDL (Hardware Description Language) and FPGA. QuartusII is used to compile and generate the function modules, RTL level description circuit and simulated waveform. RTL level description is the circuit connection in FPGA chip. It shows the connection of the modules. Simulated waveform shows us the timing and the function of the SHA-1 module. The algorithm is implied easily. And the SHA-1 module that design in this paper used less memory units and logic elements. It can be used in DSA or any protocols or secure algorithm.