A numerical study of fatigue life of copper column interconnections in wafer level packages

A copper column (CuC) interconnect technology is proposed in the nano wafer level packaging program as a chip-to-substrate interconnect solution for 20 mm by 20 mm package with 100 μm pitch. Currently thermo-mechanical reliability of solder joint continues to be a major concern due to the CTE (coefficient of thermal expansion) mismatch between chip and substrate A FEA (finite element analysis) is carried out to estimate the fatigue life of the (critical) outermost corner CuC interconnect under thermal cycling. The commercial FEA software ABAQUS is used. Since a 3D finite element model constructed using 3D solid elements requires prohibitive computational resources, a macro-micro modeling approach which is feasible for handling simulation of large packages is used. This modified approach uses a global shell-and-beam model. By using shell-to-solid submodeling technique, a finely meshed submodel of the critical CuC interconnect can be analyzed. Maximum inelastic shear strain range is then extracted to estimate the solder joint fatigue life based on Solomon´s correlation. In the current study, three CuCs with different heights are investigated. Fatigue lives of those three CuC interconnect are estimated and failure sites identified.