Pipelined fault simulation on parallel machines using the circuit flow graph

Author

Tai, Shang-E ; Bhattacharya, Debashis

Author_Institution

AT&T Bell Lab., Allentown, PA, USA

fYear

1993

fDate

3-6 Oct 1993

Firstpage

564

Lastpage

567

Abstract

A new technique to parallelize fault simulation for combinational digital circuits, suitable for message passing based parallel processors, is described. Speedup is achieved via combined use of data flow analysis and pipeline-like communication between processors. Unlike previous algorithms based on fault partitioning only, this approach uses both circuit and fault partitioning, and is both memory- and time-efficient with increasing number of processors

Keywords

circuit analysis computing; combinational circuits; fault diagnosis; flow graphs; logic partitioning; logic testing; parallel algorithms; pipeline processing; processor scheduling; circuit partitioning; combinational digital circuits; data flow analysis; fault partitioning; fault simulation; message passing based parallel processors; pipeline-like communication; Circuit faults; Circuit simulation; Concurrent computing; Data analysis; Flow graphs; Frequency; Laboratories; Message passing; Parallel machines; Partitioning algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393314

Filename

393314

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2598724