DocumentCode
2599108
Title
Package optimization of a stacked die flip chip based test package
Author
Pohl, Jens ; Graml, Markus ; Strobel, Peter ; Steiner, Rainer ; Pressel, Klaus ; Stoeckl, Stephan ; Ofner, Gerald ; Lee, Charles
Author_Institution
Infineon Technol. AG, Regensburg
fYear
2004
fDate
8-10 Dec. 2004
Firstpage
590
Lastpage
594
Abstract
We report a case study for the optimization of a flip chip based stacked die array test package. We demonstrate the importance of package substrate design and substrate thickness on the processibility and package warpage control. We found that for thin substrates copper balancing of the top and bottom die is crucial. We show the impact of flip chip die thickness and substrate thickness on the die attach of the top die(s) in the stack. Investigations on different top die attach alternatives show that tape die attach can have advantages. We demonstrate the importance of the vertical stack structure (i.e. flip chip thickness) and material selection (i.e. mold compound) on the overall warpage control of the package. The results show that even small changes in the package structure can have large impact on the warpage characteristics of the stacked die package
Keywords
chip scale packaging; copper; flip-chip devices; microassembling; optimisation; stacking; substrates; Cu; die attach; flip chip based test package; flip chip die thickness; material selection; package optimization; package substrate design; package warpage control; stacked die array test package; substrate thickness; vertical stack structure; Assembly; Bonding; Design optimization; Electronics packaging; Flip chip; Microassembly; Packaging machines; Testing; Thickness control; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th
Conference_Location
Singapore
Print_ISBN
0-7803-8821-6
Type
conf
DOI
10.1109/EPTC.2004.1396676
Filename
1396676
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