Chip-in-substrate package, CiSP, technology

Author

Chen, Yu-Hua ; Lin, Jyh-Rong ; Chen, Shoulung ; Cheng-Ta Ko ; Kuo, Tzu-Ying ; Chien, Chien-Wei ; Yu, Shan-Pu ; Ostmann, Andreas ; Neuma, Alexander

Author_Institution

Ind. Technol. Res. Inst., Hsinchu

fYear

2004

fDate

8-10 Dec. 2004

Firstpage

595

Lastpage

599

Abstract

The structure of chip-in-substrate package, CiSP, is shown. The thin chips (50mum) are bonded on the organic substrate (BT) flatly. Subsequently, the chips are covered among the build-up dielectric layer, which can be either a RCC (resin coated copper) material or an organic dielectric material (ABF) by a lamination process. Via holes on the chip´s I/O pad and substrate are drilled by laser. The interconnection between chip and substrate is created by Cu without bump. The main issue is focused on the interfaces among different materials. This shorter interconnection can match the demand for fast electrical response application. At the same time, the stresses simulation for the interfaces or each key location in a CiSP is also investigated to optimize the manufacturing processes

Keywords

chip scale packaging; copper; integrated circuit interconnections; integrated circuit manufacture; laser beam machining; optimisation; simulation; 50 micron; Cu; chip I-O pad; chip-in-substrate package; interconnection; lamination process; laser drilling; manufacturing process optimization; organic substrate; stresses simulation; Bonding; Copper; Dielectric materials; Dielectric substrates; Lamination; Optical materials; Organic materials; Packaging; Resins; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th

Conference_Location

Singapore

Print_ISBN

0-7803-8821-6

Type

conf

DOI

10.1109/EPTC.2004.1396677

Filename

1396677