Efficient verification of symmetric concurrent systems

Author

Ip, C. Norris ; Dill, David L.

Author_Institution

Dept. of Comput. Sci., Stanford Univ., CA, USA

fYear

1993

fDate

3-6 Oct 1993

Firstpage

230

Lastpage

234

Abstract

Previously (Proc. 11th Symp. on Computer Hardware Description Languages and their Application, April 1993), we proposed a reduction technique based on symmetries to alleviate the state explosion problem in automatic verification of concurrent systems. This paper describes the results of testing the technique on a wide range of algorithms and protocols, including realistic multiprocessor synchronization algorithms and cache coherence protocols. Memory requirements were reduced by amounts ranging from 83% to over 99%, and time requirements were often reduced as well. We also consider the effectiveness of the technique on different types of symmetries, such as symmetries in identical system components and symmetries in data values

Keywords

cache storage; formal verification; logic CAD; memory protocols; multiprocessing systems; synchronisation; automatic verification; cache coherence protocols; data values; identical system components; memory requirements; multiprocessor synchronization algorithms; reduction technique; state explosion problem; symmetric concurrent systems; symmetries; Binary decision diagrams; Boolean functions; Computer science; Data structures; Protocols; State-space methods; Sun; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393375

Filename

393375