DocumentCode
2599700
Title
A reconfiguration-based yield enhancement system
Author
Narasimhan, J. ; Nakajima, K.
Author_Institution
IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1993
fDate
3-6 Oct 1993
Firstpage
224
Lastpage
228
Abstract
An approach to yield enhancement of programmable array chips by logical restructuring of circuit placements was recently proposed by Kumar et al. (1991). and a graph model for its reconfiguration aspect was later introduced by Narasimhan et al. (1991). Using this model and a new cost measure, we present a complete yield enhancement system. We implement two reconfiguration algorithms on it, evaluate their performances, and propose good reconfiguration strategies
Keywords
graph theory; integrated circuit layout; programmable logic arrays; reconfigurable architectures; algorithm performance; circuit placements; cost measure; graph model; logical restructuring; programmable array chips; reconfiguration strategies; reconfiguration-based yield enhancement system; Circuits; Costs; Electronics packaging; Logic arrays; Logic programming; Phased arrays; Programmable logic arrays; Routing; Semiconductor device measurement; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-4230-0
Type
conf
DOI
10.1109/ICCD.1993.393376
Filename
393376
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