Bit-splitting for testability enhancement in scan-based design

Author

Xie, Xiaodong ; Albicki, Alexander

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1993

fDate

3-6 Oct 1993

Firstpage

155

Lastpage

158

Abstract

A new design for testability technique, the bit-splitting for testability enhancement in scan-based design, is presented. The idea is to split some inputs into two independent variables to make the original circuit more controllable and thus more testable. Theoretical study and experiments with two-level circuits indicate that this method can easily provide 100% Single-Path-Sensitization Path Delay Fault Testability (SPDFT). Fault coverage can also be improved for the multi-level circuits and when constrained transformations are used, multi-level circuit can also be made 100% SPDFT

Keywords

combinational circuits; delays; design for testability; integrated circuit design; logic testing; network synthesis; SPDFT; Single-Path-Sensitization Path Delay Fault Testability; bit-splitting for testability enhancement; combinational circuit; constrained transformations; design for testability; experiments; multi-level circuits; scan-based design; two-level circuits; Circuit faults; Circuit testing; Combinational circuits; Costs; Delay; Design for testability; Electric variables control; Hazards; Performance evaluation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-4230-0

Type

conf

DOI

10.1109/ICCD.1993.393389

Filename

393389