Feature detection and matching on an SIMD/MIMD hybrid embedded processor

Author

Nieto, A. ; Vilariño, D.L. ; Brea, V.M.

Author_Institution

Centro de Investig. en Tecnoloxias da Inf. (CITIUS), Univ. of Santiago de Compostela, Santiago de Compostela, Spain

fYear

2012

fDate

16-21 June 2012

Firstpage

21

Lastpage

26

Abstract

This work presents the implementation of a feature detection and matching algorithm on an innovative SIMD/MIMD dynamically-reconfigurable architecture intended for high-performance embedded vision systems. An FPGA-based system-on-chip with a 128-unit coprocessor running at 150 MHz is able to locate a target in 320 × 240 px images in less than 1 ms. It is also shown how to map the algorithms to speedup the processing taking advantage of the different available computation modes.

Keywords

computer vision; coprocessors; embedded systems; feature extraction; field programmable gate arrays; image matching; parallel architectures; reconfigurable architectures; system-on-chip; 128-unit coprocessor; FPGA-based system-on-chip; SIMD-MIMD dynamically-reconfigurable architecture; SIMD-MIMD hybrid embedded processor; feature detection algorithm; feature matching algorithm; high-performance embedded vision systems; Arrays; Coprocessors; Databases; Feature extraction; Hip; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Vision and Pattern Recognition Workshops (CVPRW), 2012 IEEE Computer Society Conference on

Conference_Location

Providence, RI

ISSN

2160-7508

Print_ISBN

978-1-4673-1611-8

Electronic_ISBN

2160-7508

Type

conf

DOI

10.1109/CVPRW.2012.6238890

Filename

6238890