Configurable microcontroller array

Author

Maslennikov, Oleg ; Shevtshenko, Juri ; Sergyienko, Anatoli

Author_Institution

Tech. Univ. of Koszalin, Poland

fYear

2002

fDate

2002

Firstpage

47

Lastpage

49

Abstract

In this paper, the configurable microcontroller array based on the i8051 processor unit (PU) architecture is proposed. The use of the well-known PU architecture simplifies the application programming. The designed microcontroller PU core has in 6 times higher instruction implementation speed, and in more than 2.5 times clock frequency than the original microcontroller. The proposed technique of mapping the program into configurable hardware showed the 1.5-2-fold hardware minimization. It shows an effective way to speedup the implementation of both computing and control intensive algorithms. Proposed/array is very useful in such applications, where logic intensive calculations, or high speed byte handling computations are of demand. For example, such applications are homomorphic image processing, pattern recognition, genetic algorithms, neural nets, etc.

Keywords

field programmable gate arrays; microcontrollers; parallel architectures; reconfigurable architectures; FPGA; application programming; clock frequency; configurable hardware; configurable microcontroller array; control intensive algorithms; hardware minimization; high speed byte handling computations; i8051 processor unit architecture; instruction implementation speed; logic intensive calculations; Clocks; Frequency; Genetic algorithms; Hardware; Image processing; Logic arrays; Microcontrollers; Neural networks; Pattern recognition; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Computing in Electrical Engineering, 2002. PARELEC '02. Proceedings. International Conference on

Print_ISBN

0-7695-1730-7

Type

conf

DOI

10.1109/PCEE.2002.1115196

Filename

1115196