DocumentCode
2604294
Title
Integration of DFM techniques and design automation
Author
Waring, Thomas G. ; Allan, Gerard A. ; Walton, Anthony J.
Author_Institution
Dept. of Electr. Eng., Edinburgh Univ., UK
fYear
1996
fDate
6-8 Nov 1996
Firstpage
59
Lastpage
67
Abstract
This paper reports the integration of a yield enhancing router within the Alliance design automation environment. The system converts a high level description, using a subset of VHDL, to mask layout. The final layout has been made more robust to spot defects using a number of layout modification strategies within the routing network. The results indicate that these modifications significantly reduce the probability of faults for the device as a whole
Keywords
circuit layout CAD; design for manufacture; high level synthesis; integrated circuit layout; integrated circuit yield; Alliance environment; DFM; VHDL subset; defects; design automation; fault probability; high level description; mask layout; routing network; yield; Circuit faults; Design automation; Design for manufacture; Fabrication; Integrated circuit technology; Poisson equations; Predictive models; Production; Robustness; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location
Boston, MA
ISSN
1550-5774
Print_ISBN
0-8186-7545-4
Type
conf
DOI
10.1109/DFTVS.1996.571991
Filename
571991
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