• DocumentCode
    2604828
  • Title

    SCUBA: an HDL data-path/memory module generator for FPGAs

  • Author

    Mohanty, Sidhartha ; Aheswaran, Kapilan M. ; Haruyama, Shinichiro ; Niu, Jiang

  • Author_Institution
    Lucent Technol. Inc., AT&T Bell Labs., Allentown, PA, USA
  • fYear
    1997
  • fDate
    19-22, Oct 1997
  • Firstpage
    135
  • Lastpage
    142
  • Abstract
    Lucent Technologies´ ORCA (Optimized Reconfigurable Cell Array) FPGAs, with their nibble-oriented architecture, are especially suitable for data-path-intensive circuits. The current design flows do not fully utilize the data-path and memory capabilities in the ORCA architecture. To fully utilize the capability of ORCA´s flexible data-path blocks and to provide the designer with the flexibility of accessing the architectural features of ORCA, the tool SCUBA (Synthesis Compiler for User-programmaBle Arrays) was developed and integrated into the ORCA design flow. SCUBA synthesizes parametrized data-path and memory blocks in VHDL/Verilog/EDIF, which are optimized for the ORCA architecture. SCUBA can also provide optimal positional information to a placer. By preserving regularity information of a circuit network structure in a layout tool, the performance of the synthesized circuits improves substantially. SCUBA also provides a means for exploring future-generation architectures by providing interface blocks for designing complex structures, such as application-specific blocks
  • Keywords
    circuit layout CAD; field programmable gate arrays; hardware description languages; high level synthesis; reconfigurable architectures; EDIF; FPGA; Lucent Technologies; ORCA; Optimized Reconfigurable Cell Array; SCUBA; VHDL; Verilog; application-specific blocks; circuit network structure; data-path-intensive circuits; data-path/memory module generator; design flows; flexible data-path blocks; future-generation architectures; interface blocks; memory capabilities; nibble-oriented architecture; optimal positional information; regularity information; synthesis compiler; synthesized circuit performance; user-programmable arrays; Circuit synthesis; Costs; Design engineering; Digital signal processing; Field programmable gate arrays; Hardware design languages; Integrated circuit synthesis; Logic circuits; Network synthesis; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VHDL International Users' Forum, 1997. Proceedings
  • Conference_Location
    Arlington, VA
  • Print_ISBN
    0-8186-8180-2
  • Type

    conf

  • DOI
    10.1109/VIUF.1997.623942
  • Filename
    623942