Physical Model for NAND operation in SOI and Body-Tied Nanocrystal FinFLASH memories

Author

Perniola, L. ; Nowak, E. ; Iannaccone, G. ; Scheiblin, P. ; Jahan, C. ; Pananakakis, G. ; Razafindramora, J. ; Salvo, B. De ; Deleonibus, S. ; Reimbold, G. ; Boulanger, F.

Author_Institution

CEA/LETI-Mmatec, Grenoble

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

943

Lastpage

946

Abstract

Here we present a semi-analytical model for nanocrystal-based (NCs) FinFLASH memories under uniform stress: Fowler-Nordheim (FN) write/erase, gate disturb and data retention are addressed. This model is able to catch the essential features related to the non-uniform trapped charge distribution in such a complex 3D structure. Both body tied and SOI devices are included in the model. Main conclusions are related to the different characteristic times of charge trapping over fin corners or planar fin regions: double dynamics during programming, intrinsic disturb immunity of written state in FF cells. The aspect ratio impact on DeltaV_TH is also evaluated showing a slightly better performance of body tied devices.

Keywords

MOSFET; NAND circuits; flash memories; memory architecture; nanoelectronics; nanostructured materials; semiconductor device models; silicon-on-insulator; tunnelling; Fowler-Nordheim write-erase model; SOI; Si-JkJk; aspect ratio impact; body-tied nanocrystal FinFLASH memories; data retention; gate disturbance; intrinsic disturb immunity; nonuniform trapped charge distribution; physical NAND operation model; uniform stress condition; Dielectrics; Dynamic programming; Electrostatics; Immune system; Nanocrystals; Reservoirs; Stress; Transmission line matrix methods; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4419108

Filename

4419108