A model for VLSI implementation of CNN image processing chips using current-mode techniques

Author

Espejo, S. ; RodriguezVazquez, A. ; DominguezCastro, R. ; Linares, B. ; Huertas, J.L.

Author_Institution

Dept. of Analog Circuit Design, Seville Univ., Spain

fYear

1993

fDate

3-6 May 1993

Firstpage

970

Abstract

A new cellular neural network model is proposed. It allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature extraction, noise filtering, compound component detection, etc.) using the cellular neural network paradigm. Area evaluation for the new model shows a reduction of about 50% as compared to the use of current-mode techniques with conventional models. Experimental measurements of CMOS prototypes designed in a 1.6-μm n-well double-metal single-poly technology are reported

Keywords

CMOS integrated circuits; VLSI; cellular neural nets; feature extraction; image processing equipment; image recognition; neural chips; 1.6 micron; CNN image processing chips; area evaluation; cellular neural network model; compound component detection; current-mode techniques; feature extraction; n-well double-metal single-poly technology; noise filtering; preprocessing chips; Analog circuits; Buildings; Cellular neural networks; Feature extraction; Filtering; Image processing; Integrated circuit modeling; Semiconductor device measurement; Semiconductor device modeling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.393885

Filename

393885