A multi-phase shared bus structure for the fast Fourier transform

The multi-phase shared bus structure is proposed for the implementation of the complex data flows in fast Fourier transforms (FFTs). With multiphase techniques, the executions of the pipelines are time-skewed. Data communications between pipeline stages can be multiplexed via the shared bus. The routing area is small and independent of the routing complexity. For the 8-point butterfly at 100 MHz data rate, multi-phase implementation needs only 30% area compared to direct routing. By proper phase assignment, the processing latency can also be reduced. The latency of the 8-point FFT design example is reduced to 68%. The communication cost of the direct implementation and the proposed structure is estimated and compared