Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators

Soft errors caused by cosmic rays or alpha particles emitted from the packaging material around the chips are becoming an increasingly important challenge in reliable microprocessor design. Transistor density, and die size trends show that soft errors will gain even more importance in the future. Due to their significant overheads, most redundancy schemes are employed where the penalty incurred can be hidden in the pipeline. Most contemporary processors employ a large physical register file to hold the produced results which may reside there for a long time. The register file is a critical element of a microprocessor and is needed to be protected against soft errors. In this paper we propose an SRAM bitcell design with ability to hold a redundant copy of the data and compare the copies with built-in comparators to detect a possible mismatch. Our experimental results show that the proposed design has 34% area, 7.9% power 2% delay overheads which are further reducible and can protect the register file against Silent Data Corruption (SDC).