A universal BIST methodology for interconnects

Author

Chang, Carole ; Su, Chauchin

Author_Institution

Dept. of Electr. Eng., National Central Univ., Chung-Li, Taiwan

fYear

1993

fDate

3-6 May 1993

Firstpage

1615

Abstract

A methodology for the design and implementation of an universal interconnect built-in self test module for boundary-scan-based interconnects is proposed. Such a methodology is able to test any interconnects without knowing their connection configuration in advance. The fault-free responses of different I/O ports under the selected walking sequence of ones are studied. The faulty syndromes are enumerated for different faults, and compared with the fault-free ones. Two verification criteria are derived to verify the correctness of the nets. A universal interconnect (UI)-BIST hardware is designed, implemented, and tested

Keywords

automatic testing; boundary scan testing; built-in self test; fault diagnosis; integrated circuit interconnections; integrated circuit testing; boundary-scan-based interconnects; fault-free responses; faulty syndromes; interconnect built-in self test module; universal BIST methodology; universal interconnect BIST hardware; verification criteria; walking sequence; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design methodology; Hardware; Integrated circuit interconnections; Legged locomotion; Pins; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394048

Filename

394048