Enable++: a second generation FPGA processor

In the computing community field, programmable processors are going to fill the niche for special purpose computing devices. A typical example is ultra fast pattern recognition in experimental particle physics, a task for which we constructed two years ago (1993), Enable 1, an FPGA processor rather specialized for pattern recognition algorithms in μs domain, but also provided with modest features for coping with more general applications. The paper presents the follow up model Enable++, a 2nd generation FPGA processor that offers several substantial enhancements over the previous system for a wider range of applications: Enable++ is structured into three different state of the art modules for providing computing power, flexible and high speed I/O communication and powerful intermodule communication with a raw bandwidth of 3.2 GByte/s by an active backplane. The technical realization of all three modules is guided by the maximum usage of field programmable logic. The actual demand of computing and I/O power can be satisfied by the number of modules plugged into the crate. Enhanced features of Enable++ comprise the configurable processor topology provided by programmable crossbar switches. In combination with the 4×4 FPGA array and 12 MByte distributed RAM, the Enable++ computing core offers a strongly increased and scalable computing power. For building new applications, the system offers a comfortable programming and debugging environment consisting of a compiler for the C like hardware description language spC, a simulator and a source level debugger for hardware design