A class of zero wasted area floorplan for VLSI design

A new approach to solve the floorplan area optimization problem is proposed. Using the analogy between a floorplan and a resistive network, the length and width of an individual block of a floorplan are represented by the voltage and current of a branch in a resistive network of a certain topology. The floorplan area minimization problem becomes a resistive network synthesis problem with a given power dissipation. By applying network and graph theories, a systematic network analogy procedure is developed. Necessary and sufficient conditions for zero wasted area floorplan are also given. An optimal algorithm for solving the optimization problem is proposed by replacing the nonlinear equations with the linear ones. Experimental results show that the authors´ algorithm is efficient and can handle a large floorplan successfully