DocumentCode
2611533
Title
Modified probabilistic RAM architecture for VLSI implementation of a backpropagation learning algorithm
Author
Lee, Eel-Wan ; Won, Jae-Hee ; Chae, Soo-Ik
Author_Institution
Dept. of Electron. Eng., Seoul Nat. Univ., Seoul, South Korea
fYear
1993
fDate
3-6 May 1993
Firstpage
1897
Abstract
A network based on the modified probabilistic RAM architecture is proposed for VLSI implementation with on-chip learning capability. The pRAM structure is modified for the computation of error backpropagation and weight updates, where the multiplication and summations are performed with simple AND gates and OR gates, respectively. The simulation results for the derived algorithm are discussed, and a VLSI implementation of the pRAM for backpropagation is also explained
Keywords
VLSI; backpropagation; neural chips; probabilistic logic; random-access storage; AND gates; OR gates; VLSI; backpropagation learning algorithm; error backpropagation; multiplication; pRAM structure; probabilistic RAM architecture; summations; weight updates; Backpropagation algorithms; Computer architecture; Electronic mail; Error correction; Network-on-a-chip; Neurons; Optical computing; Phase change random access memory; Random number generation; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394119
Filename
394119
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