DocumentCode
2611676
Title
Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman´s Algorithm
Author
Véstias, Mário ; Neto, Horácio
fYear
2012
fDate
5-8 Sept. 2012
Firstpage
782
Lastpage
788
Abstract
Financial and commercial applications depend on decimal arithmetic since the results must match exactly those obtained by human calculations. Multiplication and squaring are frequently used operations in these applications. In this paper we propose to improve the efficiency of state-of-the-art decimal multipliers using the Karatsuba-Ofman´s algorithm. The method is also used to implement the squaring operation. The results indicate that the proposed parallel decimal multipliers based on the Karatsuba-Ofman´s algorithm are very efficient with area reductions up to 30%. Also, the proposed decimal squarers achieve improvements in the area of almost 40% compared to a multiplier for the same number of digits, stressing the importance of dedicated implementations of these units.
Keywords
field programmable gate arrays; multiplying circuits; FPGA; Karatsuba-Ofman´s algorithm; decimal arithmetic; human calculation; parallel decimal multiplier; parallel decimal squarer; Adders; Algorithm design and analysis; Complexity theory; Equations; Hardware; Mathematical model; Standards; Decimal Multiplication; Decimal Squaring; Decimal arithmetic; FPGA;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design (DSD), 2012 15th Euromicro Conference on
Conference_Location
Izmir
Print_ISBN
978-1-4673-2498-4
Type
conf
DOI
10.1109/DSD.2012.101
Filename
6386973
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