A new column redundancy scheme for fast access time of 64-Mb DRAM

Author

Jun, Young-Hyun ; Jeong, Weon-Hwa ; Park, Jong-Hoon ; Kim, Tae-Hoon ; Kim, Seong-Wook ; Lee, Jae-Sik ; Jang, Seong-Jin ; Khang, Chang-Man ; Lee, Hee-Gook

Author_Institution

GoldStar Electron Central Res. Lab., Seoul, South Korea

fYear

1993

fDate

3-6 May 1993

Firstpage

1937

Abstract

A 3.3-V 64-Mbit DRAM is fabricated using 0.4-μm CMOS triple poly and double metal process technology. The DRAM implements a new column redundancy scheme called the data line suppression (DLS) to achieve fast access time. The widely used redundancy method for DRAMs (the address suppression scheme) has the disadvantage that access time for the redundancy column is longer than the normal column. The new DLS scheme overcomes this problem. A full chip 64-Mb DRAM which incorporates the new redundancy scheme is designed and successfully fabricated. Measurements confirm that column access time (t_AA) for both the normal and redundant column are identical. It is 27 ns for typical operating conditions

Keywords

CMOS memory circuits; DRAM chips; VLSI; integrated circuit design; integrated circuit technology; redundancy; 0.4 micron; 27 ns; 3.3 V; 64 Mbit; DRAM; access time; address suppression scheme; column redundancy scheme; data line suppression; double metal process technology; operating conditions; triple poly process technology; CMOS process; CMOS technology; Circuits; Delay effects; Electrons; Fuses; Laboratories; Random access memory; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394129

Filename

394129