200 mega pixel rate IDCT processor for HDTV applications

Author

Kim, Chan S. ; Song, Sang W. ; Kim, Man Y. ; Han, Young T. ; Kang, Sang A. ; Lee, Bang W.

Author_Institution

Samsung Electronic Co., Buchun, Kyung Gi-Do, South Korea

fYear

1993

fDate

3-6 May 1993

Firstpage

2003

Abstract

A high-speed video rate 8 × 8 inverse discrete cosine transform (IDCT) processor using a distributed arithmetic architecture is presented. 64-point one-dimensional IDCT processing units are simultaneously operated with 8 clock cycles. With these 64 fully parallel units and three-stage pipeline structure for each unit, the latency time of this proposed architecture is only 37 cycles. ROM banks containing IDCT coefficients are minimized to 12 by applying two pixel bits per clock. This VLSI is fabricated in 1.0-μm double metal CMOS process with 120 mm² die area. It consumes approximately 3 watts at a 5 volt operating voltage and 50 MHz master clock frequency. Since critical path delay is given as 15.5 nsec, this proposed chip has enough speed for digital HDTV applications

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; discrete cosine transforms; high definition television; pipeline processing; video signal processing; 1.0 micron; 15.5 ns; 3 W; 5 V; 50 MHz; HDTV applications; ROM banks; VLSI; critical path delay; distributed arithmetic architecture; double metal CMOS process; inverse discrete cosine transform; latency time; master clock frequency; one-dimensional IDCT processing units; operating voltage; three-stage pipeline structure; Arithmetic; CMOS process; Clocks; Delay; Discrete cosine transforms; HDTV; Pipelines; Read only memory; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394146

Filename

394146