• DocumentCode
    2612048
  • Title

    Parallel regeneration of interconnections in VLSI & ULSI circuits

  • Author

    Nekili, Mohamed ; Savaria, Yvon

  • Author_Institution
    Dept. of Electr. Eng., Ecole Polytech. of Montreal, Que., Canada
  • fYear
    1993
  • fDate
    3-6 May 1993
  • Firstpage
    2023
  • Abstract
    The problem of how to efficiently regenerate long interconnections in VLSI and ULSI circuits is addressed. The necessary conditions to regenerate an interconnection are first established. Then, the concept of parallel regeneration is suggested as a novel method that performs much better than conventional methods. It is shown that this method has a property already encountered with conventional methods, i.e., the invariance of the regenerator design versus line length
  • Keywords
    CMOS integrated circuits; VLSI; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; ULSI; VLSI; invariance; line length; long interconnections; parallel regeneration; regenerator design; Delay effects; Integrated circuit interconnections; Integrated circuit technology; Inverters; Logic; Propagation delay; Ultra large scale integration; Very large scale integration; Voltage; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
  • Conference_Location
    Chicago, IL
  • Print_ISBN
    0-7803-1281-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.1993.394151
  • Filename
    394151