Si nanowire device and its modeling

Because of its nature of effectively suppressing the off-leakage current with gate around configuration, the Si nanowire FET has been thought be the ultimate structure for for ultra-small CMOS devices towards their downsizing limit. Recently, several experimental data of Si nanowire FETs with very high on-current much larger than that of planar MOSFETs have been published. Thus, Si nanowire FETs are now drawing attention as the most promising candidate for the mainstream CMOS devices in 2020s. In order for the Si nanowire FETs to be introduced into integrated circuits, good compact models which circuit designers can easily handle with are essential. However, it is a really challenging task to establish the compact model, because I_d-V_d characteristics of the Si nanowire FETs are affected by the band structure of the nanowire, and the band structure are very sensitive with the nanowire diameter, cross-sectional shape, crystal orientation, mechanical stress, and interface states. In this paper, recent research status of Si nanowire FETs in experimental and theoretical works are described.