A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI

Author

Kuo, J.B. ; Chen, H.P. ; Huang, H.J.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1993

fDate

3-6 May 1993

Firstpage

2027

Abstract

A race-free BiCMOS dynamic divider circuit using a non-restoring iterative architecture with carry look ahead is presented. Using the BiCMOS dynamic circuit, an 8-bit ÷ 4-bit divider test circuit, based on 2-μm BiCMOS technology, shows more than 4.5 times improvement in speed as compared to the CMOS divider circuit. The speed advantage of the BiCMOS dynamic divider circuit is even greater in a 64-bit divider, which is helpful for CPU VLSI

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; VLSI; carry logic; dividing circuits; hazards and race conditions; 2 micron; 4 bit; 64 bit; 8 bit; carry look ahead; dynamic divider circuit; nonrestoring iterative architecture; race-free BiCMOS; speed advantage; Artificial intelligence; BiCMOS integrated circuits; CMOS technology; Central Processing Unit; Circuit testing; Logic circuits; Logic devices; Logic gates; MOS devices; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394152

Filename

394152

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2612085