Gate array placement based on mincut partitioning with path delay constraints

Author

Wakabayashi, Shin´ichi ; Kusumoto, Hiroshi ; Mishima, Hideki ; Koide, Tetsushi ; Yoshida, Noriyoshi

Author_Institution

Fac. of Eng., Hiroshima Univ., Higashi-Hiroshima, Japan

fYear

1993

fDate

3-6 May 1993

Firstpage

2059

Abstract

Two placement methods for VLSI gate array layout considering interconnection delay are proposed. One is a fast iterative improvement algorithm, and the other is a simulated-annealing-based algorithm. Both the proposed methods directly treat timing constraints, each of which is given to a pair of pins in the circuit. Experimental results confirm the effectiveness of the proposed methods

Keywords

VLSI; circuit layout CAD; circuit optimisation; delays; integrated circuit interconnections; iterative methods; logic CAD; logic arrays; logic partitioning; simulated annealing; timing; VLSI gate array; fast iterative improvement algorithm; gate array placement; interconnection delay; mincut partitioning; path delay constraints; placement methods; simulated-annealing-based algorithm; timing constraints; Capacitance; Circuit simulation; Delay; Integrated circuit interconnections; Iterative algorithms; Pins; Simulated annealing; Timing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394161

Filename

394161