Power optimized high level synthesis of Multiply-and-Accumulate (MAC) based digital filter architectures under SNR constraints

The optimum word length selection for arithmetic circuits in VLSI implementation is crucial in optimizing the design for area and power. This paper proposes a scheme for further word length optimization (WLO) using system level parameters such as dynamic range and SNR. A scaled fixed point (SFXP) representation is discussed, which has advantages of both fixed point and floating point. The dynamic range and noise aspects of chosen representation are simulated using MATLAB. The results show only 1 dB SNR degradation for signals with SNR of 17 dB, when a 15 bit ADC output is represented with (3,4) SFXP representation. To illustrate the suitability of the proposed WLO scheme under practical signal conditions, a Multiply-and-Accumulate (MAC) unit is realized with SFXP representation for simulation and synthesis studies. Power saving up to 20% is observed for Xilinx´s Spartan 6 FPGAs, in comparison with conventional MAC implementation. Algorithm for high level synthesis (HLS) of MAC units from signal flow graph (SFG) with proposed SFXP representation is presented.