DocumentCode
2612454
Title
A two-pole circuit model for VLSI high-speed interconnection
Author
Zhou, D. ; Su, S. ; Tsui, F. ; Gao, D.S. ; Cong, J.S.
Author_Institution
EE Dept., North Carolina Univ., Charlotte, NC, USA
fYear
1993
fDate
3-6 May 1993
Firstpage
2129
Abstract
A high-speed VLSI interconnection is modeled by using a generic distributed-RLC tree. Through a detailed analysis of the distributed-RLC tree a two-pole approximation system is established. Relating the solution of the two-pole approximation to the interconnection geometric parameters, a VLSI performance-driven layout problem is formulated which reveals the interplay between the interconnection performance and its geometrical parameters
Keywords
VLSI; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; network topology; VLSI; generic distributed-RLC tree; high-speed interconnection; interconnection geometric parameters; performance-driven layout problem; two-pole approximation system; two-pole circuit model; Capacitance; Distributed parameter circuits; Impedance; Integrated circuit interconnections; Integrated circuit modeling; Performance analysis; RLC circuits; Tree data structures; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394178
Filename
394178
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