• DocumentCode
    2613590
  • Title

    Implementation of high order matched filter on a FPGA chip

  • Author

    Xu, Yankai ; Shuang, Kai

  • Author_Institution
    Coll. of Geophys. & Inf. Eng., China Univ. of Pet. (Beijing), Beijing, China
  • Volume
    5
  • fYear
    2011
  • fDate
    15-17 Oct. 2011
  • Firstpage
    2526
  • Lastpage
    2530
  • Abstract
    The paper reviews derivation of matched filter. Particular attention has been paid to design and implementation of matched filter. In the paper a receiver system with matched filter for a deterministic signal is constructed and simulated in matlab/simulink. The distributed arithmetic (DA) based high-order matched filter on field programmable gate array (FPGA) device is implemented.
  • Keywords
    digital filters; field programmable gate arrays; matched filters; mathematics computing; FPGA chip; Matlab; Simulink; deterministic signal; distributed arithmetic based high-order matched filter; field programmable gate array device; high order matched filter; Equations; Filtering theory; Finite impulse response filter; Matched filters; Maximum likelihood detection; Receivers; FPGA; Matched filter; Simulation; distributed arithmetic; implementation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Image and Signal Processing (CISP), 2011 4th International Congress on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-9304-3
  • Type

    conf

  • DOI
    10.1109/CISP.2011.6100756
  • Filename
    6100756
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2613590