An algorithm for loop delay estimation in digital predistortion system

In this paper, an algorithm for precisely estimating loop delay in digital predistortion (DPD) system is proposed. The proposed algorithm consists of integer loop delay estimation and fractional loop delay estimation. Compared with conventional algorithms, the integer loop delay can be estimated using improved algorithm based on Euclidean distance function while the fractional loop delay estimation is modified by iterative method. Simulation results prove the validity of the proposed loop delay estimation method and the effect on the DPD system. Furthermore, the proposed algorithm requires less hardware resources.