Speed-area optimized FPGA implementation for Full Search Block Matching

This paper presents an FPGA based hardware design for full search block matching (FSBM) based motion estimation (ME) in video compression. The significantly higher resolution of HDTV based applications is achieved by using FSBM based ME. The proposed architecture uses a modification of the sum-of-absolute-differences (SAD) computation in FSBM such that the total number of additions/subtraction operations is drastically reduced. This successfully optimizes the conflicting design requirements of high throughput and small silicon area. Comparison results demonstrate the superior performance of our architecture. Finally, the design of a reconfigurable block matching hardware has been discussed.