• DocumentCode
    2616939
  • Title

    An approach to low-cost fabrication of lateral COOLMOS structures

  • Author

    Shahrjerdi, D. ; Hekmatshoar, B. ; Khakifirooz, A. ; Fathipour, M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
  • fYear
    2003
  • fDate
    10-12 Dec. 2003
  • Firstpage
    272
  • Lastpage
    273
  • Abstract
    The main building block of COOLMOS device is a combination of parallel n- and p- strips, which is called as superjunction. Unique capability of the superjunction is an efficient sustained voltage when the transistor is in OFF-state. This paper presents the fabrication of the lateral COOLMOS structures on SOI substrate. Dessis simulator has been employed to characterize the COOLMOS structure. The depletion region edge during ON-state operation of COOLMOS structure is depicted. The n+ source region is formed by resist-masked implantation of antimony, followed by annealing to activate the dopants.
  • Keywords
    annealing; antimony; ion implantation; power MOSFET; semiconductor device models; SOI substrate; Sb; Si; annealing; antimony; cost reduction; depletion region edge; lateral COOLMOS structure fabrication; low-cost fabrication; on-chip realization; resist-masked implantation; superjunction; sustained voltage; Annealing; Boron; Costs; Epitaxial growth; Fabrication; MOSFETs; Strips; Substrates; Tungsten; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Device Research Symposium, 2003 International
  • Print_ISBN
    0-7803-8139-4
  • Type

    conf

  • DOI
    10.1109/ISDRS.2003.1272093
  • Filename
    1272093
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2616939