Design of a MCML Gate Library Applying Multiobjective Optimization

Author

Pereira-Arroyo, Roberto ; Alvarado-Moya, Pablo ; Krautschneider, Wolfgang H.

Author_Institution

Costa Rica Inst. of Technol.

fYear

2007

fDate

9-11 March 2007

Firstpage

81

Lastpage

85

Abstract

In this paper, the problem of sizing MOS current mode logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 mum technology are presented.

Keywords

MOS logic circuits; Pareto optimisation; circuit optimisation; current-mode logic; genetic algorithms; logic design; 0.35 micron; MCML gate library; MOS current mode logic circuits; Pareto front; design space exploration; fitness functions; genetic algorithm; multiobjective optimization; output voltage swing; postlayout simulations; propagation delay; Aggregates; Design optimization; Energy consumption; Genetic algorithms; Libraries; Logic circuits; Pareto analysis; Power measurement; Space exploration; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Conference_Location

Porto Alegre

Print_ISBN

0-7695-2896-1

Type

conf

DOI

10.1109/ISVLSI.2007.38

Filename

4208898