Modeling Subthreshold Leakage Current in General Transistor Networks

An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements. The occurrence of on-switches in off-networks, ignored by previous works, is considered in the proposed static current analysis. This leakage model has been validated through electrical simulations, taking into account a 130nm process, with good correlation of the results.