Notch elimination in polycide gate stack etching for advanced DRAM technology

Author

Chan, Bor-Wen ; Chi, Min-Hwa ; Liou, Y.H.

Author_Institution

Center for Technol. Dev., Worldwide Semicond. Manuf. Corp., Hsinchu, Taiwan

fYear

2000

fDate

2000

Firstpage

133

Lastpage

139

Abstract

The notch phenomenon in etching of complex TEOS/oxynitride/WSi_x/poly DRAM gate stacks is eliminated by adding N₂ gas in the poly over-etch (OE) step. The N₂ addition in poly OE can passivate poly surface against Cl-atom attack; however, it also results in increasing poly residues. Therefore, by increasing the over-etch time of WSi_x etching, these residues can be removed. The optimized recipe can achieve both residue-free and notch-free processing with no impact on the critical dimensions (CD) of the gate stack and remaining oxide after etching

Keywords

DRAM chips; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; surface contamination; surface topography; Cl-atom attack; DRAM technology; N₂; N₂ gas addition; Si; SiO₂-SiON-WSi-Si; TEOS/oxynitride/WSi_x/poly DRAM gate stacks; WSi; WSi_x etching; critical dimensions; etching; gate stack; notch elimination; notch phenomenon; notch-free processing; optimized recipe; over-etch time; poly over-etch step; poly residues; poly surface passivation; polycide gate stack etching; residue removal; residue-free processing; Etching; Plasma applications; Plasma chemistry; Plasma devices; Plasma materials processing; Plasma sources; Radio frequency; Random access memory; Resists; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Technology Workshop, 2000

Conference_Location

Hsinchu

Print_ISBN

0-7803-6374-4

Type

conf

DOI

10.1109/SMTW.2000.883094

Filename

883094