Modeling of direct tunneling current through interfacial SiO2 and high-K gate stacks

As MOSFET device dimensions continue to scale down, a SiO₂ gate of less than 2.0 nm is required. At these thicknesses, a large direct tunneling current will flow between the gate electrode and the silicon substrate, which increase standby power consumption and reduces device performance. Therefore, high-K gate dielectrics with equivalent oxide thickness but larger physical thickness have been investigated as replacements for SiO₂. In this work, quantum mechanical calculations are employed for the inversion layer in p-type Si substrates and a modified WKB approximations for the transmission probability to model direct tunneling currents.