DocumentCode
2618726
Title
XGD: an automatic gate level schematic design system. 1
Author
Lau, K.M. ; Andrade, H.A. ; Wiley, C. ; Wu, C.-L.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
452
Abstract
An automatic schematic design system called XGD which produces highly readable schematics at the gate level through a graphical, user-friendly, user-configurable design environment is described. The four major parts of the system are described. An overview of the algorithms for building the network graph and placing the gates is given. The pseudocode for the functions to read in the input file and build the graph are presented, along with the gate placement functions. The pseudocode of compaction functions implemented in the system is given. The system implementation and an example are discussed
Keywords
circuit layout CAD; logic CAD; user interfaces; CAD; XGD; automatic schematic design system; compaction functions; computer aided logic design; gate level; gate placement functions; network graph; user-configurable design environment; user-friendly; Chip scale packaging; Design automation; Feedback circuits; Feedback loop; Libraries; Object oriented programming; Programming profession; Routing; Sun; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112079
Filename
112079
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