VLSI-placement with a neural network model

Author

Zhang, Chen-Xiong ; Mlyinski, D.A.

Author_Institution

Inst. fuer Theor. Elektrotech. und Messtech., Karlsruhe Univ., West Germany

fYear

1990

fDate

1-3 May 1990

Firstpage

475

Abstract

A placement algorithm based on an extension of neural network models suggested by T. Kohonen (1982) and H. Ritter (1986) is proposed. The approach combines the characteristics of the placement problem with the mapping property of a neural model. The relation between movable modules and slots on a chip is met by an algorithm able to establish topology maps between an input space (sensory source) and an output space (cortical area). The neural network model is programmed in C language and implemented on a VAX 11/750 computer. The results obtained seem to exceed those of classical placement algorithms like force-directed relaxation and simulated annealing in efficiency and computation time

Keywords

VLSI; circuit layout CAD; network topology; neural nets; C language; CAD; IC layout design; VAX 11/750 computer; VLSI-placement; mapping property; neural network model; placement algorithm; topology maps; Circuits; Computational modeling; Computer networks; Hopfield neural networks; NP-complete problem; Network topology; Neural networks; Simulated annealing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112087

Filename

112087