Modeling and Implementation of an All Digital Phase-Locked-Loop for Grid-Voltage Phase Detection

In this paper, a novel all digital phase-locked-loop (ADPLL) is proposed for the phase detection of power grid voltage. The proposed ADPLL features wide track-in range and fast pull-in time, and it can be easily integrated into the digital controller with low cost. The nonlinear model of such digital system is derived from the operation principle of the ADPLL and the linearized model is then obtained to evaluate the steady and dynamic performance due to the nonlinear and discrete property. Compared with the conventional DPLL, the proposed ADPLL has almost no steady state phase error when the frequency of the input signal deviates from the center frequency. Moreover, the tracking speed is highly improved. In contrast with other ADPLLs, the proposed one employs the loop filter with proportional-Integral (PI) structure, which can help to eliminate the steady state error excited by high-order disturbances or noise. As a result, a low system clock or sampling frequency is enough to get a satisfactory performance, which is an attractive advantage for the low cost applications. Simulation and experimental results verify the analysis and the effectiveness of the ADPLL.