3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier

Author

Kousai, Shouhei ; Onizuka, Kohei ; Yamaguchi, Toru ; Kuriyama, Yasuhiko ; Nagaoka, Masami

Author_Institution

Toshiba, Kawasaki, Japan

fYear

2014

fDate

9-13 Feb. 2014

Firstpage

58

Lastpage

59

Abstract

One of the ultimate goals in power amplifier design is to enhance the effective efficiency and achieve a long battery life. Therefore, both the peak efficiency and the efficiency loss due to antenna impedance mismatch or power back-off are highly critical design issues. In particular, the challenge of the antenna impedance mismatch is becoming more severe, due to the increased frequency band and smaller antenna size. Moreover, the antenna mismatch also changes with time due to the user proximity effect [1].

Keywords

CMOS analogue integrated circuits; antennas; impedance matching; power amplifiers; 3G-4G CMOS power amplifier design; antenna impedance mismatch; antenna size; efficiency loss; polar antenna impedance detection; polar antenna impedance tuning; power back-off; user proximity effect; Antennas; Detectors; Impedance; Impedance measurement; Power amplifiers; Tuners;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4799-0918-6

Type

conf

DOI

10.1109/ISSCC.2014.6757336

Filename

6757336