DocumentCode
262068
Title
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
Author
Fluhr, Eric J. ; Friedrich, J. ; Dreps, Daniel ; Zyuban, V. ; Still, Gregory ; Gonzalez, Christopher ; Hall, Asha ; Hogenmiller, D. ; Malgioglio, Frank ; Nett, Ryan ; Paredes, J. ; Pille, J. ; Plass, Donald ; Puri, R. ; Restle, Phillip ; Shan, David ; Sta
Author_Institution
IBM STG, Austin, TX, USA
fYear
2014
fDate
9-13 Feb. 2014
Firstpage
96
Lastpage
97
Abstract
The 12-core 649mm2 POWER8™ leverages IBM´s 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor Vts are used for power/performance tuning, and thick-oxide transistors enable high-voltage I/O and analog designs. The 15-layer BEOL contains 5-80nm, 2-144nm, 3-288nm, and 3-640nm pitch layers for low-latency communication as well as 2-2400nm ultra-thick-metal (UTM) pitch layers for low-resistance distribution of power and clocks.
Keywords
DRAM chips; microprocessor chips; silicon-on-insulator; 12-core server-class processor; BEOL; IBM eDRAM SOI technology; POWER8; UTM; analog designs; capacitance 31.5 muF; deep-trench decoupling capacitance; high-voltage I/O; low-latency communication; low-resistance distribution; microarchitectural enhancements; off-chip bandwidth; power-performance tuning; size 22 nm; size 32 nm; socket performance; thin-oxide transistor; transistors; ultra-thick-metal pitch layers; Arrays; Bandwidth; Clocks; Hardware; Random access memory; Transistors; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4799-0918-6
Type
conf
DOI
10.1109/ISSCC.2014.6757353
Filename
6757353
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