Design and realization of a two input fuzzy chip running at a rate of 80 ns

Author

Falchieri, D. ; Gabrielli, A. ; Gandolfi, E. ; Masetti, M.

Author_Institution

Dipartimento di Fisica, Bologna Univ., Italy

fYear

1997

fDate

21-24 Sep 1997

Firstpage

329

Lastpage

334

Abstract

A VLSI fuzzy chip with two 7 bit inputs has been designed to run at a rate of 80 ns. The chip has been designed in 0.7 μm CMOS technology and to reach such a speed the architecture is pipelined and only the active rules are processed. The design uses the VHDL as a front-end tool and has been synthesized by the Cadence Opus SW obtained via Europractice using the cell-based digital 0.7 μm CMOS ES2 technology library. The chip has been sent to the ES2 foundry to be constructed. The chip size is 14 square mm. The chip has been designed for high energy physics applications

Keywords

CMOS logic circuits; VLSI; fuzzy logic; hardware description languages; high energy physics instrumentation computing; integrated logic circuits; logic CAD; CMOS ES2 technology library; CMOS technology; Cadence Opus SW; Europractice; VHDL; VLSI fuzzy chip; active rules; front-end tool; high energy physics applications; pipelined architecture; two input fuzzy chip design; CMOS process; CMOS technology; Frequency selective surfaces; Fuzzy reasoning; Fuzzy sets; Fuzzy systems; Input variables; Physics; Pipelines; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Fuzzy Information Processing Society, 1997. NAFIPS '97., 1997 Annual Meeting of the North American

Conference_Location

Syracuse, NY

Print_ISBN

0-7803-4078-7

Type

conf

DOI

10.1109/NAFIPS.1997.624061

Filename

624061