• DocumentCode
    262114
  • Title

    7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network

  • Author

    Cong Shi ; Jie Yang ; Ye Han ; Zhongxiang Cao ; Qi Qin ; Liyuan Liu ; Nan-Jian Wu ; Zhihua Wang

  • Author_Institution
    Chinese Acad. of Sci., Beijing, China
  • fYear
    2014
  • fDate
    9-13 Feb. 2014
  • Firstpage
    128
  • Lastpage
    129
  • Abstract
    A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the von Neumann bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.
  • Keywords
    high-speed techniques; image processing; image sensors; neural nets; parallel processing; PE array; dynamically reconfigurable hybrid architecture; high-speed compact vision system; image sensor; parallel image processors; pixel-parallel processors; row-parallel SIMD array processors; self-organizing map neural network; single silicon die; vision chip; Arrays; Face recognition; Image processing; Neural networks; Neurons; Program processors; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4799-0918-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2014.6757367
  • Filename
    6757367