Highly integrated system-on-chip circuits for the readout of high-energy physics detectors

Summary form only given. The very high particle rates and multiplicities that will be produced by the ultra-relativistic hadron collider at LHC, CERN, have set new demands on the readout electronics in terms of resolution, density, speed, complexity and power consumption. These requirements, which are beyond the present capability of commercial-off-the-shelf components, could only be met by highly integrated systems implemented with very deep submicron CMOS technologies. These technologies not only offer speed, density, and computational power, but also radiation tolerance. The potential upgrade of the LHC and other newly planned facilities, e.g. the International Linear Collider (ILC), set even more demanding requirements, which call for ASICs that embed in a single chip the circuits to amplify, digitize, process, compress and store the information of a high number of channels. This paper reviews some examples of highly integrated single-chip circuits developed for the LHC Experiments, and will discuss the role that future silicon processes may play on the on-detector readout and signal processing electronics for future experiments.